The invention relates to scan-based debugging and, in particular, to an integrated circuit with scan-based debugging with help of an embedded in-circuit emulator.
Currently, silicon diagnosis methods in integrated circuit technology often used are visual inspection by electron beam probing, direct physical contact with probe needles, and dedicated debug registers to display signal states for debugging. It is also common to share debug ports with normal functional pins under debug mode and use a logic analyzer to determine the status of an internal circuit.
FIG. 1 is a schematic diagram of a conventional debugging method of an integrated circuit disclosed in U.S. Pat. No. 6,687,865. A service processor unit (SPU) 101 is incorporated in an integrated circuit 100 and coupled to a system bus 105 and an added test bus 104. Test wrappers 102 are connected to the test bus 104 to provide test communication channels into selected blocks 106. The SPU 101 provides a connection for an external diagnostic console 103 to view and test the internal workings of the integrated circuit 100.
Required instructions are stored in a system SRAM. The SPU 101 follows the instructions in the system SRAM and transfers test patterns stored in the system SRAM to a certain portion of user defined logic. Thereafter, test results are serially transferred from the logic and analyzed by the SPU 101. In other words, the PSU 101 provides a specific pattern to a specified logic and analyze outcome thereof, similar to ATPG. All operations of the SPU 101 are performed with scan chains in the integrated circuit 100.
U.S. Pat. No. 6,687,865 also discloses a built-in logic analyzer utilized to capture internal signal states and the captured data are stored in the system SRAM. The captured data can be accessed by a diagnostic console 103 via existing test ports.
The SPU provides test patterns and analyzes the test results. The SPU, however, deals only with a specified portion of user-defined logic. In addition, data accessed by the diagnostic console via the test interface is probed by the built-in logic analyzer.